1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and, more particularly, to a semiconductor integrated circuit including a write controlling circuit.
2. Related Art
Generally, most semiconductor memory manufacturing companies have developed a phase change random access memory (PRAM) that employs phase change materials and is a next generation memory device that adheres to the current trend of memory device designs that highly enhance the performance of a semiconductor integrated circuit and to lower power consumption thereof. The PRAM is a non-volatile memory device that stores data by using a material such as GexSbyTez (hereinafter, referred to as “GST”), in which the resistance of the GST varies through phase change according to temperature variation.
In more detail, a unit memory cell of the PRAM can store data by setting one of two physical states based on the difference in the resistivity of the GST. In other words, high resistance of the GST represents a value of ‘1’, and low resistance of the GST represents a value of ‘0’, so that digital information can be written. Such reversible phase change of the GST of the PRAM is achieved by adjusting the time and the voltage of an electrical pulse signal applied from an external device. Therefore, the electrical resistance state of the GST is arbitrarily controlled so that data can be stored. Meanwhile, in order to change the phase of a highly-integrated PRAM cell array, a pulse signal activated under a desirable voltage and for desirable time is required in a write operation.